Effects of gate Bias Stressing in Power VDMOSFETs

Abstract

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon ≡Si_o^• defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxidetrapped charge buildup, while subsequent hole tunnelling from the charged oxide traps ≡Si_o⁺ to interface-trap precursors ≡Si_s-H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects ≡Si_o^••Si_o≡ is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors ≡Si_s−Η with the charged oxide traps ≡Si_o^+•Si_o≡ and H⁺ ions are proposed to be responsible for interface trap buildup.