An Analysis of Cache Configuration’s Impacts on the Miss Rate of Big Data Applications Using Gem5

Abstract

This work aims to analyze the impacts of cache configurations on miss rates of big data benchmarks with varying level 1 instruction (L1I) and data (L1D) caches using the gem5 simulator. The cache miss rate of nine big data applications from four benchmark suits is analyzed with different cache configurations, such as increasing the cache size, varying the associativity, and altering the line size. The gem5 provides a versatile platform for conducting detailed experiments. The study sheds light on the relationship between cache and big data workloads, thus offering insights into optimizing cache configurations’ effect on miss rates for improved performance.